Chemical mechanical polishing (CMP) is widely used in integrated circuit (IC) manufacturing as a method of removing material to enable the planarization of a surface of the IC. This planarization may enable accurate photolithography or improve other IC processing steps. The CMP process may involve two aspects: a chemical reaction and a physical abrasion of material. To remove material, the CMP process may use a polishing pad in a polishing apparatus. The polishing pad or the workpiece may be rotated during this CMP process. In one instance, the workpiece surface is brought into contact with a rotating pad saturated with at least one of a slurry of abrasive particles or a reactive solution that will chemically react with features on the workpiece surface. In one instance, this may be performed while exerting a force between the workpiece and polishing pad.
CMP is used for planarization, feature formation, or damascene interconnect formation. Planarization may include an oxide CMP of the pre-metal dielectric (PMD) before the formation of any contacts. Feature formation may include shallow trench isolation (STI) formation. Damascene interconnect formation may include tungsten “plug” contact formation or copper “trench” or “via” interconnect formation. In one particular example, copper metal, including the “overburden,” or excess material, is deposited by electroplating and annealed prior to a CMP process. The anneal is performed to initiate grain growth of the copper because large grain growth may reduce copper resistivity. The location of the copper may affect grain size, or the average grain diameter. The “overburden” tends to grow large grains where it is unrestricted structurally. But the copper in the trenches and vias is structurally limited, so it will grow smaller grains. Thus, large grain size of the copper on or in the trenches and vias may be induced through an anneal.
CMP processes have several shortcomings. First, localized dishing may occur. FIG. 1 is a cross-sectional view of a metal layer where localized dishing has occurred to illustrate a drawback of the prior art. The metal layer 401, which may be copper, tungsten, or some other metal, is disposed in layer 400. This layer 400 may be an interlayer dielectric (ILD) or intermetal dielectric (IMD), such as, for example, silicon oxide. The layer 400 also may be a low-k dielectric such as Si—O—C. The layer 400 and metal layer 401 will polish differently due to the difference in the properties of each.
Furthermore, during a CMP process, two different metals may be polished at the same time. A metal, such as tantalum or a nitride, may be used as a liner or diffusion barrier 413 for the metal layer 401. The liner or diffusion barrier 413 may be needed to prevent the metal in the metal layer 401 from diffusing into the layer 400. During the CMP process, the metal layer 401 and liner or diffusion barrier 413 may be polished at the same time. The difference in density and hardness of each material will cause the polish rate to vary with each material. The metal layer 401 will preferentially polish. This may cause excessive copper to be removed from the metal layer 401, creating a cavity 405 compared to an ideal surface represented by the line 406 and reducing the effective metal layer 401 thickness.
Second, dishing or microloading may occur. FIG. 2 is a cross-sectional view of a metal layer where dishing has occurred to illustrate a drawback of the prior art. Metal layer 402 is wider compared to metal layer 403. Both metal layer 402 and 403 are copper in this instance, but also may be other metals. Wide metal lines, such as metal layer 402, polish more than narrow metal lines, such as metal layer 403, causing more metal to be removed from wide metal areas and rendering it thinner. Wider metal lines, such as metal layer 402, have larger grains because these metal lines are less restricted structurally by the trench or via compared to narrow metal lines, such as metal layer 403. A CMP process on metal layers with smaller grains may involve the slurry chemistry attacking the higher density grain boundaries or the interface between two different metals. A CMP process on metal layers with larger grains may involve the slurry acting as an abrasive. Thus, wider metal lines with larger grains, such as metal layer 402, tend to polish at a different or faster rate than the narrower metal lines, such as metal layer 403. A larger cavity 407 will form compared to an ideal surface represented by line 406 in wider metal layer 402 compared to the cavity 408 for narrower metal layer 403. With all else being equal, the wider metal lines, such as metal layer 402, with larger grains will dish more.
Third, erosion may occur. FIG. 3 is a cross-sectional view of a metal layer where erosion has occurred to illustrate a drawback of the prior art. The loading effect of a CMP process will polish dense areas, such as region 411 of metal lines 404, at different rates than isolated features, such as region 412 of metal lines 404. Metal lines 404, which may be copper or some other metal, and layer 400, which may be an ILD or IMD, is removed or polished more during a CMP process if the metal lines 404 are densely situated because denser areas are more prone to erosion. Therefore, a larger cavity 410 will form compared to an ideal surface represented by line 406 in region 411 than the cavity 409 for region 412.
Fourth, a CMP process tends to have a faster polish rate or to polish more at the center of a workpiece than at an edge of a workpiece due to the way the CMP process is performed. The edge of the polishing pad may compress differently than the center of the polishing pad, causing leading edge thickness variations in the workpiece. For example, during oxide polishing, the edges of the workpiece will be polished at a slower rate or will be polished less than the center of the workpiece. This is typically compensated for by a counter profile during a chemical vapor deposition (CVD) process or an electroplating process for metal deposition.
CMP processes that are performed on metals have many drawbacks. While these examples specifically discuss copper, other metals and materials, such as dielectrics, suffer from similar problems. With the advent of scaling, the problems caused by CMP processes, such as dishing, recess, erosion, or CMP non-uniformities, become more detrimental because of the sensitivity of resistance to the thickness of a metal.
First, the results of a CMP process are not uniform across a workpiece. Rather, there are variations between dies after a CMP process. This means there will be reliability differences between different dies on the same workpiece. Certain ICs subject to a CMP process may even fail due to the results of the CMP process. Furthermore, a single CMP process may cause approximately 2-4% yield loss and sometimes up to 20% non-conformity loss due to these problems. Yield loss is a determination of whether dies on a wafer are “good” or “bad.” The “good” dies are considered part of the yield. Conformity loss is any error in an IC that does not give the desired shape or form. For example, if a cross-section of a dielectric is supposed to be planar, but after a CMP process has dishing, then the IC is a conformity loss.
Accordingly, there is a need in the art for a process to address the above-described inadequacies and shortcomings and, more particularly, an implantation process that will improve the results of a CMP process.